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| MOSEL VITELIC V53C518165A 1M x 16 EDO PAGE MODE CMOS DYNAMIC RAM OPTIONAL SELF REFRESH HIGH PERFORMANCE Max. RAS Access Time, (tRAC) Max. Column Address Access Time, (tCAA) Min. Extended Data Out Page Mode Cycle Time, (tPC) Min. Read/Write Cycle Time, (tRC) 50 50 ns 25 ns 20 ns 84 ns 60 60 ns 30 ns 25 ns 104 ns Features s 1MB x 16-bit organization s EDO Page Mode for a sustained data rate of 50 MHz s RAS access time: 50, 60 ns s Dual CAS Inputs s Low power dissipation s Read-Modify-Write, RAS-Only Refresh, CAS-Before-RAS Refresh * Refresh Interval: 1024 cycles/16 ms s Available in 42-pin 400 mil SOJ and 44/50-pin 400 mil TSOP-II Packages s Single 5V 10% Power Supply s TTL Interface s Optional Self Refresh (V53C518165AS) * Refresh Interval: 1024 cycles/128 ms Description The V53C518165A is a 1048576 x 16 bit highperformance CMOS dynamic random access memory. The V53C518165A offers Page mode operation with Extended Data Output. The V53C518165A has symmetric address, 10-bit row and 10-bit column. All inputs are TTL compatible. EDO Page Mode operation allows random access up to 1024 x 16 bits, within a page, with cycle times as short as 20ns. These features make the V53C518165A ideally suited for a wide variety of high performance computer systems and peripheral applications. Device Usage Chart Operating Temperature Range 0C to 70C -40C to +85C Package Outline K * * Access Time (ns) 50 * * Power Std. * * T * * 60 * * Temperature Mark Blank I V53C518165A Rev. 1.1 January 1998 1 MOSEL VITELIC 42-Pin Plastic SOJ PIN CONFIGURATION Top View VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS V53C518165A 44/50-Pin Plastic TSOP-II PIN CONFIGURATION Top View VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 NC NC NC WE RAS NC NC A0 A1 A2 A3 VCC 1 2 3 4 5 6 7 8 9 10 11 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 36 35 34 33 32 31 30 29 28 27 26 511816500-02 VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 NC NC LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS Pin Names A0-A9 RAS UCAS LCAS WE OE I/O1-I/O16 VCC VSS NC Row, Column Address Inputs Row Address Strobe Column Address Strobe/Upper Byte Control Column Address Strobe/Lower Byte Control Write Enable Output Enable Data Input, Output +5V Supply 0V Supply No Connect Description TSOP-II SOJ Pkg. T K Pin Count 44/50 42 V53C518165A Rev. 1.1 January 1998 2 MOSEL VITELIC Absolute Maximum Ratings* Symbol VN VDQ TBIAS TSTG V53C518165A Parameter Power Supply Voltage Input/Output Voltage Temperature Under Bias Storage Temperature Commercial -1 to +7 -0.5 to min (VCC+0.5, 7.0) -10 to +125 -55 to +125 Extended -1 to +7 -0.5 to min (VCC+0.5, 7.0) -65 to +135 -65 to +150 Units V V C C *Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Capacitance* TA = 25C, VCC = 5 V 10%, VSS = 0 V, f = 1 MHz Symbol CIN1 CIN2 COUT Parameter Address Input RAS, UCAS, LCAS, WE, OE Data Input/Output Min. -- -- -- Max. 5 7 7 Unit pF pF pF *Note: Capacitance is sampled and not 100% tested. Block Diagram I/O1 I/O2 *** I/O16 Data In Buffer WE LCAS UCAS 16 Data Out Buffer 16 OE No. 2 Clock Generator 10 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 10 Column Address Buffers (10) 10 Column Decoder Refresh Controller Sense Amplifier I/O Gating Refresh Counter (10) 10 Row Address Buffers (10) 10 Row Decoder 1024 Memory Array 1024 x 1024 x 16 1024 x16 16 RAS No. 1 Clock Generator Voltage Down Generator VCC VCC (internal) 316516500-03 V53C518165A Rev. 1.1 January 1998 3 MOSEL VITELIC DC and Operating Characteristics (1-2) TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, tT = 2ns, unless otherwise specified. Access Time Commercial Min. -10 V53C518165A Extended Min. -10 Symbol ILI ILO Parameter Input Leakage Current (any input pin) Output Leakage Current (for High-Z State) Max. 10 Max. 10 Unit Test Conditions mA mA VSS VIN VCC + 0.5V VSS VOUT VCC+ 0.5V RAS, CAS at VIH tRC = tRC (min.) Notes 1 -10 10 -10 10 1 ICC1 VCC Supply Current, Operating VCC Supply Current, TTL Standby VCC Supply Current, RAS-Only Refresh VCC Supply Current, EDO Page Mode Operation VCC Supply Current, during CAS-before-RAS Refresh VCC Supply Current, CMOS Standby 50 60 130 115 2 200 180 2 mA 2, 3, 4 ICC2 ICC3 mA RAS, CAS at VIH other inputs VSS tRC = tRC (min.) 2, 4 50 60 50 60 50 60 130 115 50 40 130 115 1.0 200 180 90 75 200 180 1.0 mA ICC4 mA Minimum Cycle 2, 3, 4 ICC5 mA tRC = tRC (min.) 2, 4 ICC6 mA RAS VCC - 0.2 V, CAS VCC - 0.2 V other input VSS CBR cycle with tRAS tRASS (min.), CAS Held Low, WE = VCC-0.2V, Address and DIN = VCC-0.2V or 0.2V 1 ICC7 Self Refresh (Optional) 250 250 mA VCC VIL VIH VOL VOH Power Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 4.5 -0.5 2.4 5.5 0.8 VCC+0.5 0.4 4.5 -0.5 2.4 5.5 0.8 VCC+0.5 0.4 V V V V V IOL = 4.2 mA IOH = -5.0 mA 1 1 1 1 2.4 2.4 V53C518165A Rev. 1.1 January 1998 4 MOSEL VITELIC TA = 0C to 70C, VCC = 5 V 10%, tT = 2ns, unless otherwise noted Limit Values -50 # Symbol Parameter Min. Max. Min. -60 V53C518165A AC Characteristics(5,6) Max. Unit Note Common Parameters 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period 84 30 50 8 0 8 0 8 12 10 13 40 5 1 -- -- -- 10k 10k -- -- -- -- 37 25 -- -- -- 50 16 104 40 60 10 0 10 0 10 14 12 15 50 5 1 -- -- -- 10k 10k -- -- -- -- 45 30 -- -- -- 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7 Read Cycle 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 tRAC tCAC tCAA tOAC tCAR tRCS tRCH tRRH tCLZ tOFF tOEZ tDZC tDZO tCDD tODD Access time from RAS Access time from CAS Access time from column address OE access time Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay Output turn-off delay from OE Data to CAS low delay Data to OE low delay CAS high to data delay OE high to data delay -- -- -- -- 25 0 0 0 0 0 0 0 0 10 10 50 13 25 13 -- -- -- -- -- 13 13 -- -- -- -- -- -- -- -- 30 0 0 0 0 0 0 0 0 13 13 60 15 30 15 -- -- -- -- -- 15 15 -- -- -- -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 11 11 8 12 12 13 13 14 14 8, 9 8, 9 8,10 V53C518165A Rev. 1.1 January 1998 5 MOSEL VITELIC AC Characteristics (Cont'd) Limit Values -50 # Symbol Parameter Min. Max. Min. -60 V53C518165A Max. Unit Note Write Cycle 31 32 33 34 35 36 37 tWCH tWP tWCS tRWL tCWL tDS tDH Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time 8 8 0 8 8 0 8 - - - - - - - 10 10 0 10 10 0 10 - - - - - - - ns ns ns ns ns ns ns 16 16 15 Read-modify-Write Cycle 38 39 40 41 42 tRWC tRWD tCWD tAWD tOEH Read-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE command hold time 113 64 27 39 10 - - - - - 138 77 32 47 13 - - - - - ns ns ns ns ns 15 15 15 EDO Page Mode Cycle 43 44 45 46 47 48 49 tHPC tCP tCPA tCOH tRASP tRHPC tOES EDO page mode cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in EDO page mode CAS precharge to RAS Delay OE setup time prior to CAS 20 8 - 5 50 27 5 - - 27 - 200k - - 25 10 - 5 60 32 5 - - 32 - 200k - - ns ns ns ns ns ns ns 7 EDO Page Mode Read-Modify-Write Cycle 50 51 tPRWC tCPWD EDO page mode read-write cycle time CAS precharge to WE 58 41 - - 68 49 - - ns ns CAS-before-RAS Refresh Cycle 52 53 54 55 56 tCSR tCHR tRPC tWRP tWRH CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns CAS-before-RAS Counter Test Cycle 57 tCPT CAS precharge time (CAS-before-RAS counter test cycle) 35 - 40 - ns V53C518165A Rev. 1.1 January 1998 6 MOSEL VITELIC Limit Values -50 # Symbol Parameter Min. Max. Min. -60 V53C518165A Max. Unit Note Optional Self Refresh 58 59 60 61 tREF tRASS tRPS tCHS Self Refresh period RAS pulse width RAS precharge time CAS hold time -- 100K 95 -50 128 -- -- -- -- 100K 110 -50 128 -- -- -- ms ns ns ns 17 17 17 V53C518165A Rev. 1.1 January 1998 7 MOSEL VITELIC Notes: 1. All voltage are referenced to VSS. 2. ICC1, ICC3, ICC4, and ICC5 depend on cycle rate. 3. ICC1 and ICC4 depend on output loading. Specified values are measured with the output open. V53C518165A 4. Address can be changed once or less while RAS = VIL. In the case of ICC4 it can be changed once or less during an EDO page mode cycle. 5. An initial pause of 200 ms is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6. AC measurements assume tT = 2ns. 7. VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8. Measured with the specified current load and 100pF at VOL = 0.8 V and VOH = 2.0 V. Access time is determined by the latter of tRAC, tCAC, tCAA, tCPA, tOAC, tCAC is measured from tristate. 9. Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tCAA. 11. Either tRCH or tRRH must be satisfied for a read cycle. 12. tOFF (max.), tOEZ (max.) define the time at which the outputs acheive the open-circuit condition and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13. Either tDZC or tDZO must be satisfied. 14. Either tCDD or tODD must be satisfied. 15. tWCS, tRWD, tCWD, and tAWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.), the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if tRWD > tRWD (min.), tCWD > tCWD (min.), and tAWD > tAWD (min.), the cycle is a read-write cycle and I/O pins will contain data read from the selected cells. If neither of the above sets of conditions is satisfied, the condition of the I/O pins (at access time) is indeterminate. 16. These parameters are referenced to the CAS leading edge in early write cycles and to the WE leading edge in read-write cycles. 17. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row addresses are being refreshed on an evenly distributed manner over the refresh interval using CBR refresh cycles, then only one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in any other manner (ROR - Distributed/Burst; or CBR-Burst) over the refresh interval, then a full set of row refreshes must be performed immediately before entry to and immediately after exit from Self Refresh. V53C518165A Rev. 1.1 January 1998 8 MOSEL VITELIC Waveforms of Read Cycle t RC t RAS VIH RAS VIL t CSH t RCD UCAS LCAS VIH VIL t RAD t ASR VIH Address VIL Row Column t RCH t RAH VIH WE VIL t CAA t OAC t RCS t RRH Row t ASC t CAH t CAR t ASR t RSH t CAS t CRP t RP V53C518165A VIH OE VIL t DZC t DZO t CDD t ODD I/O (Inputs) VIH VIL t CAC t OEZ Valid Data Out t RAC t OFF I/O (Outputs) VOH Hi Z VOL t CLZ Hi Z "H" or "L" 511816502-04 V53C518165A Rev. 1.1 January 1998 9 MOSEL VITELIC Waveforms of Write Cycle (Early Write) tRC tRAS VIH RAS VIL tCSH tRCD UCAS LCAS VIH VIL tRAD tASR VIH Address Row VIL tCWL tRAH VIH WE VIL tWCH tRWL VIH OE VIL tDH tWCS tWP Column tASC tCAH tCAR tASR tRSH tCAS tCRP tRP V53C518165A . Row tDS I/O (Inputs) VIH Valid Data In VIL I/O (Outputs) VOH Hi Z VOL "H" or "L" 511816502-05 V53C518165A Rev. 1.1 January 1998 10 MOSEL VITELIC Waveforms of Write Cycle (OE Controlled Write) tRC tRAS VIH RAS VIL tCSH tRCD tRSH tCAS V53C518165A tRP tCRP UCAS LCAS VIH VIL t RAD t ASR VIH t ASC t CAH t CAR t ASR Row tCWL Address Row VIL t RAH VIH Column tRWL tWP WE VIL tOEH VIH OE VIL tDZO tDZC I/O (Inputs) VIH Valid Data VIL tCLZ tOAC VOH I/O (Outputs) Hi-Z VOL Hi-Z tOEZ tODD tDH tDS "H" or "L" 511816502-06 V53C518165A Rev. 1.1 January 1998 11 MOSEL VITELIC Waveforms of Read-Write (Read-Modify-Write) Cycle tRWC tRAS VIH VIL RAS tRCD UCAS LCAS VIH VIL tRAH tASR VIH Address VIL tRAD tAWD tCWD tRWD VIH WE VIL tCAA tRCS VIH OE VIL tDZO tDZC VIH I/O (Inputs) VIL Valid Data in tCLZ tCAC tOEZ I/O (Outputs) VOH VOL t RAC "H" or "L" V53C518165A tRP tCSH tRSH tCAS tCRP tCAH tASC tASR Row Column tCWL tRWL tWP Row tOAC tOEH tDS tDH tODD Data Out 511816502-07 V53C518165A Rev. 1.1 January 1998 12 MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle V53C518165A tRASP VIH t RP RAS VIL tRCD tRHPC tPC tCRP UCAS LCAS VIH VIL tRSH tCP tCAS tCAS tCRP tCAS tCSH tASR tRAH tASC tCAH tASC tCAH tCAR tASC tCAH VIH Address VIL Row tRAD Column 1 Column 2 Column N tRRH tRCS VIH tRCH WE VIL tCAC tCAA tOES tCPA tCAC tCAA tCPA tOFF VOH tOAC OE VOL tRAC tCAA tCAC VIH VIL tOEZ tCOH tCOH tCLZ Data Out 1 Data Out 2 Data Out N I/O (Output) 511816502-08 "H" or "L" V53C518165A Rev. 1.1 January 1998 13 MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle (OE Control) V53C518165A tRASP VIH tRP tRCD tRHPC RAS VIL tPC tCRP VIH tRSH tCP tCAS tCAS tCRP tCAS UCAS LCAS VIL tCSH tRAH tASC tCAH tASC tCAH tASC tCAR tCAH tASR VIH Address VIL Row tRAD Column 1 Column 2 Column N tRRH tRCS VIH tRCH WE VIL tCAC tCAA tOES tOEHC tCPA tOEHC tCAC tCAA tCPA tOFF VOH tOAC OE VOL tRAC tCAA tCAC tCLZ I/O (Output) VIH VIL tOEP tOAC tOEP tOAC tOEZ tOEZ tOEZ Data Out 1 Data Out 2 Data Out N 511816502-09 "H" or "L" V53C518165A Rev. 1.1 January 1998 14 MOSEL VITELIC Waveforms of EDO Page Mode Read Cycle (WE Control) tRASP VIH V53C518165A tRP tRCD tRHPC RAS VIL tPC tCRP VIH VIL tRSH tCP tCAS tCAS tCRP tCAS UCAS LCAS tCSH tRAH tASC tCAH tASC tCAH tASC tCAR tCAH tASR VIH Address VIL Row tRAD Column 1 Column 2 tCAA Column N tCAA tRRH tRCS VIH tRCH tRCH tRCS tRCS tRCH WE VIL tWPZ tCAC tOES VOH tWPZ tCAC tCPA tOFF tCPA tOAC OE VOL tCAR tCAA tCAC VIH VIL tOEZ tWEZ tWEZ tCLZ Data Out 1 Data Out 2 Data Out N I/O (Output) "H" or "L" 511816502-10 V53C518165A Rev. 1.1 January 1998 15 MOSEL VITELIC Waveforms of EDO Page Mode Early Write Cycle V53C518165A tRASP VIH tRP tRCD tRHPC RAS VIL tPC tCRP VIH VIL tRSH tCP tCAS tCAS tCRP tCAS UCAS LCAS tCSH tASR tRAH tASC Row Addr tRAD tCWL tWCS tWCH tWP tWCS tCWL tWCH tWP tWCS tCAH tASC tCAH tASC tCAR tCAH VIH Address VIL Column 1 Column 2 Column N tRWL tCWL tWCH tWP VIH WE VIL VOH OE VOL tDS VIH tDH tDS tDH tDS tDH I/O (Input) Data In 1 VIL Data In 2 Data In N "H" or "L" 511816502-11 V53C518165A Rev. 1.1 January 1998 16 MOSEL VITELIC Waveforms of EDO Page Mode Late Write Cycle V53C518165A tRASP VIH tRP tRCD RAS VIL tPC tCRP VIH tRSH tCP tCAS tCP tCAS tCRP tCAS UCAS LCAS VIL tCSH tRAH tASC tCAH tASC tCAH tCAR tASC tCAH tASR VIH Address VIL Row tRAD Column 1 tCWL Column 2 Column N tCWL tRWL tCWL tRCS VIH tRCS tRCS WE VIL tWP tWP tWP tOEH VOH tOEH tOEH OE VOL tODD tDS tODD I/O (Input) VIH VIL tODD tDS tDH tDS tDH tDH Data In 1 Data In 2 Data In N "H" or "L" 511816502-12 V53C518165A Rev. 1.1 January 1998 17 tRASP VIH RAS tCSH tPRWC tCP tCAS tCAS tCAR tASR tCAS tRAD tRAH tASC tASC Column tCPWD tCWD tCWL tCPWD tCWD tRWL tCWL tAWD tWP tOAC tWP tOAC Row Column tRWD tCWD tCWL tAWD tWP Column tASC tCAH tCAH tCAH tCRP tRSH tRCD tRP V53C518165A Rev. 1.1 January 1998 MOSEL VITELIC VIL UCAS LCAS VIH VIL tASR VIH Address Row VIL tRCS VIH WE tAWD tCAA tOAC Waveforms of EDO Page Mode Read-Modify-Write Cycle 18 tDZC tCLZ tDZC Data In tCLZ tCAC tRAC tOEZ tDH tDS Data Out Data Out VIL VIH OE tCPA tODD VIL tCPA tDZC Data In tCLZ tOEH tOEH tOEZ tDH tDS Data Out tODD Data In VIH tDZO I/O (Inputs) tODD tOEH tCAA VIL tCAA tCAC tOEZ tDS tDH I/O (Outputs) VOH VOL V53C518165A 511816502-13 MOSEL VITELIC Waveforms of RAS Only Refresh Cycle V53C518165A tRC tRAS VIH tRP RAS VIL tRPC UCAS LCAS VIH VIL tCRP tRAH tASR tASR VIH Address VIL Row Row I/O (Outputs) VOH HI-Z VOL 511816502-14 "H" or "L" V53C518165A Rev. 1.1 January 1998 19 MOSEL VITELIC Waveforms of CAS-before-RAS Refresh Cycle tRC tRP VIH V53C518165A tRAS tRP RAS VIL tRPC tCP UCAS LCAS VIH VIL tCRP tCSR tCHR tRPC tWRP tWRH VIH WE VIL tOEZ VIH OE VIL tCDD VIH VIL I/O (Inputs) tODD I/O (Outputs) VOH HI-Z VOL tOFF 511816502-15 "H" or "L" V53C518165A Rev. 1.1 January 1998 20 MOSEL VITELIC Waveforms of CAS-before-RAS Self Refresh Cycle (Optional) V53C518165A tRP VIH tRASS tRPS RAS VIL tRPC tCSR tCP UCAS LCAS VIH VIL tCRP tCHS tWRP tWRH VIH WE VIL VIH OE VIL tCDD VIH VIL I/O (Inputs) tODD tOEZ I/O (Outputs) VOH HI-Z VOL tOFF 511816502-15 "H" or "L" V53C518165A Rev. 1.1 January 1998 21 MOSEL VITELIC Waveforms of Hidden Refresh Read Cycle tRC tRAS tRP tRC tRAS V53C518165A tRP VIH RAS VIL tRCD tRSH tCHR tCRP UCAS LCAS VIH VIL tRAD tASC tRAH tASR tCAH tWRP tWRH tASR VIH Address VIL Row Column Row tRCS VIH tRRH WE VIL tCAA tOAC VIH OE VIL tDZC tDZO tCDD tODD I/O (Inputs) VIH VIL tCAC tCLZ tRAC tOEZ tOFF I/O (Outputs) VOH VOL Valid Data Out HI-Z "H" or "L" 511816502-16 V53C518165A Rev. 1.1 January 1998 22 MOSEL VITELIC Waveforms of Hidden Refresh Early Write Cycle tRC tRP VIH V53C518165A tRC tRAS tRP tRAS RAS VIL tRCD VIH tRSH tCHR tCRP UCAS LCAS VIL tRAD tRAH tASR tASC tCAH Column tWCS tWCH tWRP tWRH tASR VIH Address VIL Row Row VIH tWP WE VIL tDS VIH tDH I/O (Input) Valid Data VIL I/O (Output) VOH HI-Z VOL 511816502-17 "H" or "L" V53C518165A Rev. 1.1 January 1998 23 MOSEL VITELIC Notes: V53C518165A V53C518165A Rev. 1.1 January 1998 24 MOSEL VITELIC Notes: V53C518165A V53C518165A Rev. 1.1 January 1998 25 MOSEL VITELIC Notes: V53C518165A V53C518165A Rev. 1.1 January 1998 26 MOSEL VITELIC Package Diagrams 42-Pin 400 mil SOJ 1.08 -0.010 [27.41 -0.25] 42 22 .441 -0.006 [11.2 -0.15](1) 0.3700.010 [9.40.25] .441 0.006 [11.2 0.15] V53C518165A .406 -0.012 [10.3 -0.3] 1 21 0.045 [1.15] MIN .406 -0.012(1) [10.3 - 0.3] 0.008 -0.002 0.088 0.004 [2.24 0.1] +0.005 +0.12 0.2 -0.05 0.81 [.032] MAX 0.0170.004 [0.43 0.1] 0.05 [1.27] 1.0 [25.4] 0.145 [3.68] MAX 0.004 [0.1] Unit in inches [mm] (1) Does not include plastic or metal protrusion of 0.010 [0.25] max per side. 44/50-Pin 400 mil TSOP-II 0.039 0.002 [1 0.05] 0.0040.002 [0.10.05] 0.047 Max [1.2 Max] 0.4 0.005 [10.16 0.13] 0.006 -0.001 +0.08 0.15 -0.03 +0.003 0.031 [0.8] 0.016 +0.002 -0.004 0.4 +0.05 -0.1 50 40 36 26 0.008 [0.2] M 44x 0.004 [0.1] 0.0200.004 [0.5 0.1] 0.4630.008 [11.76 0.2] 1 11 15 1 25 Unit in inches [mm] 0.8250.005 [20.950.13] 1 Does not include plastic or metal protrusion of 0.010 [0.25] max. per side V53C518165A Rev. 1.1 January 1998 27 MOSEL VITELIC U.S.A. 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 WORLDWIDE OFFICES TAIWAN 7F, NO. 102 MIN-CHUAN E. ROAD, SEC. 3 TAIPEI PHONE: 011-886-2-545-1213 FAX: 011-886-2-545-1209 1 CREATION ROAD I SCIENCE BASED IND. PARK HSIN CHU, TAIWAN, R.O.C. PHONE: 011-886-35-783344 FAX: 011-886-35-792838 V53C518165A JAPAN WBG MARINE WEST 25F 6, NAKASE 2-CHOME MIHAMA-KU, CHIBA-SHI CHIBA 261-71 PHONE: 011-81-43-299-6000 FAX: 011-81-43-299-6555 HONG KONG 19 DAI FU STREET TAIPO INDUSTRIAL ESTATE TAIPO, NT, HONG KONG PHONE: 011-852-665-4883 FAX: 011-852-664-7535 U.S. SALES OFFICES NORTHWESTERN 3910 NORTH FIRST STREET SAN JOSE, CA 95134 PHONE: 408-433-6000 FAX: 408-433-0185 SOUTHWESTERN SUITE 200 5150 E. PACIFIC COAST HWY. LONG BEACH, CA 90804 PHONE: 562-498-3314 FAX: 562-597-2174 CENTRAL & SOUTHEASTERN 604 FIELDWOOD CIRCLE RICHARDSON, TX 75081 PHONE: 972-690-1402 FAX: 972-690-0341 NORTHEASTERN SUITE 436 20 TRAFALGAR SQUARE NASHUA, NH 03063 PHONE: 603-889-4393 FAX: 603-889-9347 (c) Copyright 1998, MOSEL VITELIC Inc. 1/98 Printed in U.S.A. The information in this document is subject to change without notice. MOSEL VITELIC makes no commitment to update or keep current the information contained in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of MOSEL-VITELIC. MOSEL VITELIC subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applications. MOSEL VITELIC does not do testing appropriate to provide 100% product quality assurance and does not assume any liability for consequential or incidental arising from any use of its products. If such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. MOSEL VITELIC 3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461 |
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